J A M E S   G A R L A N D  B.Eng. (Hons.), M.Sc.	

	Top Flat, 92 Cabra Park, Phibsborough, Dublin 7. Ireland.	
	Telephone. +353 (0) 1 868 5566	Mobile. +353 (0) 86 173 7766	Email. james@jpgarland.com	

Profile
	Senior IC Design Engineer with 9 years of Digital SoC / IP ASIC, FPGA and PCB design, training and customer support experience in a variety of different industries. Project manager, team and technical leader with strong interpersonal skills.	

Career History
	Lecturer / Research	Trinity College Dublin, Dublin, Ireland.	2003	-	Present	
	•	Lecturer in Embedded Hardware Design for the Ubiquitous Computing Course.
•	Specifying, designing and testing ARM / Xscale, FPGA / ASIC hardware in Verilog, PCB schematic and software drivers for a Delay Tolerant Sensor Network.
•	Proposed, specifying, designing and testing an EI Technology Development funded sensor system for obstruction detection and collision avoidance.	
						
	Senior IC Design Engineer.	ParthusCeva Inc, Dublin, Ireland.	1999	-	2003	
	•	PACE Project managed, specified, technically led and co-designed Bluetooth Verilog Digital IP for ASIC including SCAN insertion, STA and SCAN chain pattern generation. Also implemented design in FPGA.
•	Tested the IP against 3rd party devices to attain Bluetooth Qualification Board (BQB) Certification.
•	Trained and supported up to 11 key & strategic customers on and off site in the use of the IP.
•	Assisted in key customer contract negotiation.
•	Put forward patentable ideas to seek market potential.
•	Mentored a team member.
•	Interviewed and selected recruitment candidates. Fire Officer.	
						
	Digital ASIC Designer.	ARM Ltd., Cambridge. U. K.	1997	-	1999	
	•	Functional VHDL simulated / synthesised AMBA bus protocol and Micropack Design package.
•	Debugged and tested at VHDL and back annotated level the LCD controller block of the SA1100.
•	Project managed, specified, technically led and designed the VHDL LCD controller IP.
•	Co-specified a Visual Basic model of the LCD Panel for LCD controller verification.
•	Presented the LCD controller project overview to the Silicon Group.
•	Project managed, specified, technically led and designed the VHDL LCD controller block of the ARM7110. Followed design through to silicon. Used in the Psion 5MX and mobile applications.
•	Fault graded the ARM 720 and ARM740 with Zycad simulator. Amended the Zycad cell libraries; modelled the cache. Fault graded with pre-written vectors to obtain the coverage figures.	
						
	Digital ASIC Designer.	LucasVarity, Birmingham, UK.	1995	-	1997	
	•	Specified, designed, tested the Automotive Electronic Unit Injector (EUI) ASIC.
•	Designed functional vectors for the EUI.
•	Designed the test bench for the EUI in VHDL to accept assembler test vectors. Modelled where necessary design blocks for rapid testing.
•	Designed test bench / VHDL simulations for Aerospace Engine Transient Pressure Unit ASIC.
•	Built ETPU design into a ‘real’ time emulator. Connected this to hardware for system testing.
•	Specified and designed the Automotive Engine Transmission Controller ASIC in VHDL.	
Qualifications
	M. Sc. System Design (Microelectronics).	University of Central England in Birmingham. U. K.	1995	
	M. Sc. Project Placement.	Lucas Electronics, Birmingham. U. K.	1995	
	•	Specified and designed the Structural Implementation of the CAN Communications Protocol onto an ASIC Using VHDL. Presented the design to Lucas Management and University supervisors.	
				
	B. Eng. (Hons.). Engineering (Electrical & Electronic).	Coventry University.	 U. K.	1992-1994	
	•	Specified and designed an Audio Effects Signal Processor & Optic Fibre Transmission System. Presented the design to University supervisors.	
				
	H. N. D. Electrical & Electronic Engineering.	Coventry University.	 U. K.	1990-1992	

Technical Skill Set
	Design Packages.	Simulation: SystemC, Synopsys VCS, ModelSim Compiler & Simulator, Cadence Verilog-XL / NCVerilog, Vantage Compiler & Simulator;
ASIC Synthesis: SystemC, Compass Synthesiser / Schematic Capture, Cadence Schematic Capture, Synopsys DCXP;
STA: Synopsys Primetime;
ATPG: Synopsys Tetramax;
FPGA Synthesis: SystemC, Altera MaxPlus II, Exemplar Leonardo Spectrum for Altera, Xilinx Synthesiser;
FPGA Place Route: Altera Quartus;
ASIC Emulation: Quickturn Logic Animator.
PCB Schematic: Mentor PowerLogic	
	High Level Languages.	Perl, Shell Scripts, Borland Pascal, Borland C++, BASIC.	
	Low Level Languages.	Assemblers for: ARM, TMS320c25µP, 8051µC, Z80 µP.	

Work Related Training Courses
	BSM, Ireland.	PACE Core Team Leadership Workshop.	2002	
	Synopsys, Ireland.	Synopsys PrimeTime STA Training.	2002	
	Synopsys, Ireland.	Synopsys DCXP and Tetramax Training.	2002	
	Bennett, Ireland.	Bennetts Design For Test.	2001	
	Esperan, Ireland.	Esperan Verilog Course.	2000	
	ARM, U. K.	Platform LSF Cluster Training.	1999	
	ARM, U. K.	Basic Perl Training.	1999	
	Avanti, U. K.	Avanti Planet PL and Avanti Apollo.	1998	
	Synopsys, U. K.	Synopsys ASIC Synthesiser.	1998	
	Mentor, U. K.	Mentor People Skills Training.	1997 - 1998	
	Mentor, U. K.	ARM Presentation Skills.	1997	
	ARM, U. K.	ARM Training.	1997	
	Compass, France.	Compass ASIC Synthesiser.	1996	

Personal Details
	Date of Birth.	9th October 1971.	
	Marital Status.	Married.	
	Interests.	Music, 'Cello (Grade 1), Guitar, Cycling, Badminton (captain of league team), Swimming, Photography, Hiking, Computers, General & Technical Reading.	
	Other Details.	Holder of Full Clean E.C. Driving Licence.